Method for programming a single EPROM or flash memory cell to store multiple levels of data that utilizes a forward-biased source-to-substrate junction

ABSTRACT

Multiple logic levels can be programmed into a single EPROM or FLASH memory cell by applying one of a corresponding number of programming voltages to the control gate of a memory cell that has a forward-biased source-to-substrate junction and a reverse-biased drain-to-substrate junction. During programming, the bias conditions form substrate hot electrons which, in addition to the channel hot electrons, accumulate on the floating gate. By utilizing the substrate hot electrons, a much lower control gate voltage can be utilized during programming. More importantly, however, once the channel hot electrons cease to exist, the substrate hot electrons and holes converge to a stable charge that is related to the control gate voltage used during programming and the programmed threshold voltage of the cell.

RELATED APPLICATION

The present application is related to commonly-assigned U.S. patentapplication Ser. No. 08/392,087, filed by Albert Bergemont et al. ofeven ate herewith, for A METHOD FOR PROGRAMMING A SINGLE EPROM OR FLASHMEMORY CELL TO STORE MULTIPLE LEVELS OF DATA THAT UTILIZES A FLOATINGSUBSTRATE.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to floating gate memory cells and, moreparticularly, to a method for programming a single EPROM or FLASH memorycell to store multiple levels of data, i.e., more than a logic "1" and alogic "0".

2. Description of the Related Art

FIG. 1 shows a conventional n-channel, floating gate memory cell 10. Asshown in FIG. 1, memory cell 10 includes an n-type source region 12 andan n-type drain region 14 which are formed a distance apart in a p-typesubstrate 16. The surface area of substrate 16 between the source anddrain regions 12 and 14 defines a channel region 18 which is typicallydoped with additional p-type dopants (typically boron atoms) to adjustthe threshold voltage of the cell.

Formed over the channel region 18 is a stacked gate structure whichincludes a gate oxide layer 20, a polysilicon floating gate 22 formedover gate oxide layer 20, an oxide-nitride-oxide (ONO) layer 24 formedover floating gate 22, and a polysilicon control gate 26 formed over ONOlayer 24.

With 0.8 micron technology, where the channel length is approximately0.8 microns, memory cell 10 is conventionally programmed to store one oftwo logic levels, i.e., a logic "1" or a logic "0", by grounding thesource region 12 and substrate 16, applying a bias voltage VD in therange of 6-8 volts to the drain region 14, and applying a programmingvoltage VG of approximately 12 volts to control gate 26.

FIG. 2 shows the result of these bias conditions on memory cell 10. Asshown in FIG. 2, when the programming voltage is applied to control gate26, a positive potential is induced on floating gate 22. The positivepotential on floating gate 22, in turn, attracts electrons from thedoped p-type atoms in the channel region 18 to the surface of substrate16 to form a channel 30, and also repels holes from the doped p-typeimpurity atoms to form a depletion region 32.

When the bias voltage VD is applied to the drain region 14, an electricfield is established between the source and drain regions 12 and 14 inchannel region 30 and depletion region 32. The electric fieldaccelerates the electrons in channel 30 which, in turn, have ionizingcollisions that form "channel hot electrons". The positive potential offloating gate 22 attracts these channel hot electrons which penetrategate oxide layer 20 and begin accumulating on floating gate 22.

The negative charge on floating gate 22 that results from theaccumulated electrons, in turn, directly corresponds to the thresholdvoltage required to induce a defined current to flow through memory cell10. Thus, when a large negative charge has accumulated on floating gate22, the threshold voltage of the cell is large because a larger positivevoltage must be applied to control gate 26 to compensate for thenegative charge on floating gate 22. Similarly, if the cell has not beenprogrammed, the threshold voltage is small because a smaller voltagewill induce current to flow through the cell.

The above-described process is self-limiting because, as the number ofelectrons on floating gate 22 increases, the potential of floating gate22 decreases until the potential on floating gate 22 is insufficient tocreate channel 30.

When memory cell 10 is read, a reference threshold voltage is applied tocontrol gate 26 to again induce a potential on floating gate 22. Ifmemory cell 10 has not been programmed, the positive potential onfloating gate 22 will cause channel 30 to again be formed. As a result,current flows from the drain region 14 to the source region 12 throughchannel 30.

If memory cell 10 has been programmed, the potential on floating gate 22is reduced by the accumulated electrons so that a much smaller currentflows through channel 30. By then comparing the current to a referencecurrent, the magnitude of the current can be interpreted to be either alogic "1" or a logic "0". In other words, if the threshold voltage ofthe cell is larger than the reference threshold voltage, then one logiclevel is present, whereas if the threshold voltage of the cell issmaller than the reference threshold voltage, then the other logic levelis present.

Historically, the density of memory arrays has been increased byreducing the feature sizes of the cells. As the feature sizes becomeever smaller, however, this approach becomes more costly and moredifficult to implement.

Another approach to increasing the density of a memory array is toprogram each cell to store more than two logic levels. As stated above,memory cells are conventionally programmed to store one of two logiclevels, i.e., a logic "1" or a logic "0". However, if each memory cellcould be programmed to store a logic "00", "01", "10", or "11", then thedensity of an array could be doubled without changing the physical sizeof the array.

In theory, multi-level programming could be accomplished by varying thelength of time that the programming voltage is applied to the controlgate. Thus, for example, if the programming voltage was applied for afirst time period, the floating gate would reach a corresponding firstnegative charge level. Similarly, if the programming voltage was appliedfor either a second, third, or fourth time period, the floating gatewould reach either a corresponding second, third, or fourth negativecharge level.

The problem with this type of multi-level programming, however, is thatit is difficult to precisely control the number of electrons thataccumulate on the floating gate because the reduced floating gatepotential that results from the electrons accumulating on the floatinggate causes fewer electrons to be attracted to the floating gate,thereby causing the number of electrons accumulated on the floating gateto vary over time. The greater the variation, the more difficult it isto compare current levels during a read operation and determine whichlogic level is present. As a result, there is a need for a method toaccurately program a cell to store multiple logic levels.

SUMMARY OF THE INVENTION

The present invention provides a method for accurately programming asingle memory cell to store one of three or more logic levels. As aresult, rather than storing either a logic "1" or a logic "0", a singlememory cell can store, for example, either a logic "0-0", a "0-1", a"1-0", or a "1-1".

In the present invention, the memory cell includes a source formed in asubstrate, a drain formed in the substrate a distance apart from thesource, a floating gate formed over the substrate, and a control gateformed over the floating gate.

A method for programming the memory cell to store one of three or morelogic levels as one of three or more threshold voltages includes thestep of selecting one of three or more programming voltages where thethree or more programming voltages correspond to the three or morethreshold voltages. After one of the programming voltages is selected, afirst voltage is applied to the substrate, and a second voltage isapplied to the source so that the source-to-substrate junction isforward-biased. In addition, a third voltage is applied to the drain sothat the drain-to-substrate junction is reverse-biased. After this, theselected programming voltage is applied to the control gate of thememory cell for a predetermined time.

A better understanding of the features and advantages of the presentinvention will be obtained by reference to the following detaileddescription and accompanying drawings which set forth an illustrativeembodiment in which the principals of the invention are utilized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional drawing illustrating a conventionalone-micron, n-channel, floating gate memory cell 10.

FIG. 2 is a cross-sectional drawing illustrating the bias conditionsthat result when memory cell 10 is programmed.

FIG. 3 is a cross-sectional drawing illustrating an n-channel,floating-gate memory cell 100 in accordance with the present invention.

FIG. 4 is a graphical representation illustrating a cell programmingcharacterization curve.

FIG. 5 is a graphical representation illustrating the current and theamount of negative charge injected onto the floating gate for initialand final floating-gate voltages V₁ and V₂.

FIG. 6 is a graphical representation illustrating the current ofnegative charge injected onto the floating gate for initialfloating-gate voltages V₀₀ -V₁₁ and final voltage V₄.

FIG. 7 is a graphical representation illustrating a series ofexperimental results.

DETAILED DESCRIPTION

FIG. 3 shows an n-channel, floating-gate memory cell 100 in accordancewith the present invention. As described in greater detail below, one ofthree or more logic levels can be programmed into memory cell 100 byapplying one of a corresponding three or more programming voltages tothe control gate of memory cell 100 when the cell is biased to enhancethe formation of substrate hot electrons.

As shown in FIG. 3, when formed in a p-type substrate 110, memory cell100 includes an n-type source region 112, an n-type drain region 114,and a channel region 116 formed between the source and drain regions 112and 114. Channel region 116, in turn, is doped with p-type impurityatoms to adjust the threshold voltage of the cell.

Memory cell 100 also includes a first insulation layer 120 formed overchannel region 116, a floating gate 122 formed over insulation layer120, a second insulation layer 124 formed over floating gate 122, and acontrol gate 126 formed over insulation layer 124.

In accordance with the present invention, memory cell 100 is programmedto store one of three or more logic levels by forward-biasing thesource-to-substrate junction, reverse-biasing the drain-to-substratejunction, and applying one of a corresponding three or more programmingvoltages to the control gate during programming.

With 0.6 micron technology, memory cell 100 preferably utilizes a sourcevoltage which is 0.3 to 0.8 volts less than the substrate voltage, and adrain voltage which is 4 to 6 volts greater than the substrate voltage.Thus, for example, a source voltage of -0.7 volts, a drain voltage of 5volts, and a substrate voltage of 0 volts satisfy these conditions.

When more advanced technologies with smaller feature sizes are utilized,the range of preferable bias voltages can be reduced accordingly. Thus,for example, with 0.3 micron technology, memory cell 100 preferablyutilizes a source voltage which is 0.2 to 0.6 volts less than thesubstrate voltage, and a drain voltage which is 2 to 4 volts greaterthan the substrate voltage.

As a result of these bias conditions, one advantage of the presentinvention is that substantially lower voltages can be utilized toprogram cell 100 than the 12 volts that are conventionally used toprogram a cell. Thus, the method of the present invention isparticularly applicable to low-power applications.

In operation, when one of the programming voltages is applied to controlgate 126, a positive potential is induced on floating gate 122 which, inturn, attracts electrons from the doped p-type atoms in channel region116 to the surface of substrate 110 to form a channel 130. Thispotential repels holes from the doped impurity atoms and forms adepletion region 132.

When the source and drain voltages are applied, an electric field isestablished between the source and drain regions 112 and 114. Theelectric field, as with conventional programming, accelerates theelectrons in channel 130 which, in turn, have ionizing collisions thatform channel hot electrons. The positive potential on floating gate 122attracts these channel hot electrons which penetrate insulation layer120 and begin accumulating on floating gate 122.

In addition to the formation of channel hot electrons, the presentinvention utilizes the bias conditions to enhance the formation ofsubstrate hot electrons which also collect on floating gate 122. Due tothe reverse-bias across the drain-to-substrate junction, a small,essentially constant leakage current flows from drain 114 to substrate112. The leakage current results from thermally-generated minoritycarriers in the depletion region of the drain-to-substrate junctionwhere electrons are swept to drain 114 and holes are swept to substrate110 under the influence of the electric field. The magnitude of theleakage current is limited by the number of available minority carriersthat are present in substrate 110.

The number of minority carrier electrons which are present in substrate110, in turn, can be greatly increased by forward-biasing thesource-to-substrate junction. With forward-biasing, the potential energybarrier across the source-to-substrate junction is lowered. This, inturn, allows a larger number of electrons to diffuse or be injected fromsource 112 to substrate 110 than is possible under equilibriumconditions. Until saturation is reached, the larger the forward-bias,the larger the number of electrons diffusing from source 112 tosubstrate 110.

Thus, by increasing the number of minority carrier electrons insubstrate 110 as a result of the forward-biased source-to-substratejunction, the number of minority carrier electrons which are acceleratedtowards drain 114 under the influence of the electric field is alsoincreased. Some of the minority electron carriers in substrate 110 thatare accelerated by the electric field, in turn, have ionizing collisionsthat form "substrate hot electrons". The positive potential on floatinggate 122 also attracts these substrate hot electrons which penetrateinsulation layer 120 and begin accumulating on floating gate 122.

Thus, as a result of this "bi-polar transistor effect", the number ofminority carrier electrons which are accelerated towards drain 114 underthe influence of the electric field, and thereby the number of substratehot electrons that are formed, are controlled by the magnitude of theforward-bias across the source-to-substrate junction and the magnitudeof the electric field. For example, with a constant electric field, a0.3 volt forward-bias across the source-to-substrate junction will causea relatively low number of substrate hot electrons to be formed, whereasa 0.8 volt forward-bias will cause a substantially larger number ofsubstrate hot electrons to be formed.

FIG. 4 shows a graphical representation that illustrates a cellprogramming characterization curve. As shown by lines L₁ and L₂ in FIG.4, the voltage (V) on the floating gate influences the number of hotelectrons (I) that are injected onto the floating gate.

Conventionally, the primary consideration in programming memory cells isthe time required to place a defined amount of negative charge on thefloating gate of the cell. As a result, the typical memory cell isdesigned to utilize an initial floating gate voltage V₁ and a finalfloating gate voltage V₂ that are positioned on opposite sides of thepeak of the curve shown in FIG. 4, thereby taking advantage of themaximum injection of hot electrons onto the floating gate. As described,the initial floating gate voltage V₁ represents the voltage capacitivelycoupled to the floating gate from the control gate, while the finalfloating gate voltage V₂ represents the initial voltage V₁ reduced bythe accumulated negative charge.

FIG. 5 illustrates the amount of negative charge injected onto thefloating gate for initial and final voltages V₁ and V₂. As shown in FIG.5, the amount of charge injected on the floating gate can be determinedby integrating under the curve from the initial voltage V₁ at time t₀ tothe final voltage V₂ at time t₁.

More importantly, however, FIG. 5 illustrates that any variation in thetiming will cause a greater or lesser amount of negative charge to beinjected onto the floating gate. Thus, for example, if the programmingis terminated at time t₂ rather than time t₁, a greater amount of chargewill be injected.

With conventional programming, this additional (or lesser) amount ofnegative charge does not present any problems because the cell is onlybeing programmed to one of two logic levels. Thus, as long as the cellis programmed to have a minimum amount of charge, any additional chargeis acceptable.

However, with multi-level programming, the accumulation of additionalnegative charge makes it difficult to determine which logic level isrepresented by the charge. Thus, to insure that the charge is within adefined range, the timing must be precisely controlled. As stated above,this timing is very difficult to control.

The present invention achieves multiple levels of injected charge byutilizing one of a plurality of initial voltages. Since the initialvoltages are defined by the voltage capacitively coupled to the floatinggate from the control gate, the initial voltages are selected byselecting one of a plurality of control voltages.

For example, referring again to FIG. 4, voltage V₀₀, V₀₁, V₁₀, or V₁₁may be selected as the initial voltage by selecting a correspondingcontrol gate voltage. As further shown in FIG. 4, the present inventionutilizes voltage V₄ as the final voltage. The significance of utilizingvoltage V₄ as the final voltage can be seen in FIG. 6.

FIG. 6 shows a graphical representation that illustrates the amount ofnegative charge injected onto the floating gate for initial voltages V₀₀-V₁₁ and final voltage V₄. As shown in FIG. 6, the amount of negativecharge injected on the floating gate can be determined by integratingunder the curve from each of the initial voltages V₀₀ -V₁₁ at time t₀ tothe final voltage V₄ at time t₄.

FIG. 6, however, also illustrates that because the injected chargeconverges towards zero for each initial voltage V₀₀ -V₁₁, the injectedcharge is largely insensitive to timing variations. Thus, the floatinggate can still have one of a plurality of discrete levels of injectedcharge if programming is terminated anytime between time t₄ and t₅because the amount of additional charge during this time is so small.

One drawback of the approach, as described, is that the magnitude of theinjected current drops as the voltage on the floating gate approachesthe final voltage V₄ (see FIG. 4). As a result, it takes a greateramount of time to program the cell.

In accordance with the present invention, however, line L1 of FIG.4 canbe altered, as shown by line L2, by increasing the formation ofsubstrate hot electrons as described above. Thus, although the timerequired to program a memory cell in accordance with the presentinvention remains longer than conventional programming, the formation ofsubstrate hot electrons substantially narrows the time difference.

FIG. 7 shows a graphical representation that illustrates a series ofexperimental results. As shown in FIG. 7, when zero volts were appliedto the control gate, the charge on the floating gate converged to athreshold voltage (VTP) of approximately 2.5 volts from an initialthreshold voltage of 1.5 volts within approximately 2 seconds.Similarly, when one, two, and three volts were applied to the controlgate, the charge on the floating gate converged to threshold voltages ofapproximately 3.5, 4.5, and 5.5 volts, respectively, withinapproximately 2 seconds. Although an initial threshold voltage of 1.5volts was utilized in the above experiment, any initial thresholdvoltage after erase may be utilized.

Since the charge on the floating gate converges to a stable value whichcorresponds to a defined threshold voltage within approximately 2seconds, a single floating gate memory cell can be programmed to haveone of a plurality of threshold voltages by applying the correspondingvoltage to the control gate during programming. As a result, a singlefloating gate memory cell can be utilized to store two or more bits ofdata.

For example, a 0-0 could be represented by a threshold voltage of 2.5volts, while a 0-1 could be represented by a threshold voltage of 3.5volts. Similarly, a 1-0 could be represented by a threshold voltage of4.5 volts, while a 1-1 could be represented by a threshold voltage of5.5 volts.

As further shown in FIG. 7, the experimental results also show thatchanges in the control gate voltage are linearly related to changes inthe threshold voltage, i.e., a one volt increase in the control gatevoltage increases the threshold voltage by one volt. As a result, memorycell 100 is not limited to representing two bits, but can represent anynumber of bits depending on the sensitivity of the current sensedetectors utilized to discriminate one threshold voltage from another.Furthermore, even a continuous analog level can be stored in a cell as athreshold voltage.

Thus, for example, a 0-0-0 could be represented by a threshold voltageof 2.5 volts, while a 0-0-1 could be represented by a threshold voltageof 3.0 volts. Similarly, a 0-0-0-0 could be represented by a thresholdvoltage of 2.5 volts, while a 0-0-0-1 could be represented by athreshold voltage of 2.75 volts.

As shown in FIG. 7, the threshold voltages converge in about two secondswhen -0.7 volts is applied to source region 112 and 5 volts is appliedto drain region 114. The magnitude of the minority carrier injection,however, can be easily manipulated by varying the source and drainvoltage levels. Thus, more electrons can be injected from source region112 into substrate 110, thereby reducing the convergence time, byreducing the voltage on source region 112, or increasing the voltage ondrain region 114.

As stated above and as shown in FIG. 7, one advantage of the presentinvention is that each memory cell can be programmed to store multiplelevels by utilizing a programming voltage that is considerably less thanthe programming voltage typically used, i.e., less than five volts inthe present invention compared to the approximately 12 volts that areconventionally used to program a cell. In addition to providing asubstantial power savings for low power applications, such as notebookcomputers, the present invention eliminates the need to form chargepumps on memory chips to produce the programming voltage, i.e., 12volts.

As is well known, charge pumps can consume a significant area, i.e., upto 30% of the total die area of a memory chip. Thus, by eliminating theneed for charge pumps, the present invention significantly reduces thearea required for a memory cell, and therefore the cost of a memory.

The elimination of high programming voltages also leads to an increasein the density of a memory array because less isolation is requiredbetween both memory cells and the peripheral circuitry. As a result, thepresent invention substantially reduces the size of the array andperiphery circuits.

It should be understood that various alternatives to the embodiment ofthe invention described herein may be employed in practicing theinvention. For example, although the present invention has beendescribed in terms of an n-channel, floating-gate memory cell, thepresent invention equally applies to a p-channel, floating-gate memorycell.

Thus, it is intended that the following claims define the scope of theinvention and that methods and structures within the scope of theseclaims and their equivalents be covered thereby.

What is claimed is:
 1. A method for programming a single floating-gatememory cell to store one of three or more threshold voltages, the memorycell having a source formed in a substrate, a drain formed in thesubstrate a distance apart from the source, a floating gate formed overthe substrate, and a control gate formed over the floating gate, themethod comprising the steps of:selecting one of three or moreprogramming voltages as a selected programming voltage, the three ormore programming voltages corresponding to said three or more thresholdvoltages; applying a first voltage to the substrate; applying a secondvoltage to the source so that a source-to-substrate junction isforward-biased; applying a third voltage to the drain so that adrain-to-substrate junction is reverse-biased; and applying the selectedprogramming voltage to the control gate of the memory cell for apredetermined time.
 2. The method of claim 1 wherein the second voltageis less than the first voltage by 0.3 or more volts.
 3. The method ofclaim 1 wherein a maximum programming voltage is less than or equal tofive volts.
 4. The method of claim 1 wherein the predetermined time isless than or equal to two seconds.
 5. The method of claim 1 wherein thethird voltage is greater than the first voltage by two or more volts.